1. Field of the Invention
The present invention relates to an integrated circuit (IC), and more particularly, to a voltage boosting circuit and method thereof capable of efficiently boosting an input voltage at a limited level to an output voltage at an enhanced level.
2. Description of the Related Art
As the degree of integration of Large Scaled Integrated LSI circuits, commonly used in contemporary electronic devices, increases, it is desirable for the supply voltage level, i.e., input voltage applied to the device, to be decreased, in order to reduce power consumption. However, with an input voltage at a decreased level, it is often difficult to obtain the operating speed required by the LSI circuit. Integration further increases parasitic capacitance in the LSI circuit, due to long and complex metal lines formed in the chip, in turn further decreasing the input voltage level. Accordingly, the operating speed is reduced and the likelihood of malfunction is increased.
For this reason, contemporary semiconductor devices commonly include an internal voltage boosting circuit which boosts the externally provided supply voltage to generate a boosted voltage at a higher level, in order to improve operating speed and maintain a suitable operating voltage required for performing the complex and various functions associated with the device.
Conventional voltage boosting circuits are disclosed in U.S. Pat. Nos. 3,942,047, 4,271,461 and 4,016,476, the contents of which are incorporated herein by reference. Such conventional circuits are of a complex configuration and therefore, when the boosting circuit is integrated into the device, chip surface area is consumed. Furthermore, such complex conventional voltage boosting circuits are of relatively low efficiency as they can consume system power to a degree that has an adverse effect on the boosted voltage level.